Digital-to-digital code converter

ABSTRACT

The present invention relates to a digital-to-digital code converter, or decimator, which implements sinc 3  processing. The input signal (X) to the code converter comprises a series of groups, each group including a series of N digital sample values occurring at high rate (1/τ) which are converted within the converter, using sinc 3  processing, into a single digital value occurring at, for example, a (1/N)τ rate for delivery to the converter output (Y). The code converter comprises three processing stages in cascade, where each stage includes separate accumulation means, each accumulation means arranged to add, during each series of N input sample values, the signal value received by that stage from the next preceding stage. Each of the three stages further includes a separate subprocessing means for processing the resultant accumulated digital value from the associated accumulation means at the end of each group period to produce a separated processed digital value which, when combined with the processed digital values from the other stages at the end of a group period, provides a single sinc 3  processed digital value for the N input signal samples of each input group.

TECHNICAL FIELD

The present invention relates to a digital-to-digital code converter forimplementing sinc³ processing to achieve very good resolution.

DESCRIPTION OF THE PRIOR ART

There is much interest in the oversampling method of analog-to-digitalconversion since it eliminates the need for precision analog circuitsand filters. In this regard see, for example, the articles by (1) J. C.Candy et al. in IEEE Transactions On Communications, Vol. COM-29, No. 6,June 1981, at pages 815-830; (2) J. C. Candy in IEEE Transactions OnCommunications, Vol. COM-33, No. 3, March 1985 at pages 249-258; and (3)J. C. Candy in IEEE Transactions On Communications, Vol. COM-34, No. 1,January 1986 at pages 72-76. The method relies on a simple modulator toconvert signals into digital form at very high speeds. This modulationtechnique uses low pass filtering in a digital circuit and resampling ata low rate, a process that has been named "decimation". Moreparticularly, decimation transforms the digitally modulated signal fromshort words occurring at a high sampling rate to longer words at a lowerrate, e.g., Nyquist rate.

It has been found that incorporating the resampling concept into adigital filter can greatly simplify the circuits. For example, in U.S.Pat. No. 4,281,318 issued to J. C. Candy et al. on July 28, 1981, atwo-stage digital-to-digital code converter, or decimating filter, isdisclosed which receives a series of input samples at rate mf₀ andgenerates a corresponding series of output samples at rate f₀, usingoverlapping triangular accumulation. The Candy et al. patent, with itstwo-stage digital-to-digital code converter, discloses that fordecimation with sigma delta modulation, the decimating filter requiresone more stage than the modulator.

The problem in the prior art is to provide a digital-to-digital codeconverter similar to the Candy et al. patented arrangement which canachieve improved resolution in the output signal.

SUMMARY OF THE INVENTION

The problem of the prior art has been solved in accordance with thepresent invention which relates to a digital-to-digital code converterwhich includes three cascaded stages to implement sinc³ processing andallow a second stage to be used in the sigma delta modulator and therebyachieve improved resolution.

It is an aspect of the present invention to provide a digital-to-digitalcode converter, or decimator, which includes an input terminal, anoutput terminal, and processing means interconnecting the input andoutput terminals which performs sinc³ processing on each sequentialinput group of N digital sample values, received at the input terminal,to generate a representative single digital output value at a (1/N) rateat the output terminal.

Other and further aspects of the present invention will become apparentduring the course of the following description and by reference to theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 is a block diagram of a preferred digital-to-digital codeconverter arrangement in accordance with the present invention;

FIG. 2 illustrates typical clock signals for the code converter of FIG.1;

FIGS. 3-13 graphically illustrate how each sample of an exemplarysequential 8-sample input group is weighted overall at separate pointsin the three stages of the digital-to-digital code converter of FIG. 1to generate the sinc³ processed associated output signal value; and

FIG. 14 graphically illustrates how each of the single output signalvalues of the code converter of FIG. 1 is generated from the overallweighting of each exemplary 8-sample serially received input group inaccordance with the overall weighting diagrams of FIGS. 3-13.

DETAILED DESCRIPTION

FIG. 1 illustrates a preferred arrangement of a digital-to-digital codeconverter or decimator 10 in accordance with the present invention,which preferred arrangement includes three cascaded stages 11, 12, and13 to implement sinc³ processing of each group of N samples of an inputsignal. For purposes of definition, it is to be understood that eachsample is described as a digital word which may comprise any number ofbits. Hereinafter, however, it will be assumed that each input wordcomprises only one bit which has either a zero or a one value, butlonger words will appear at other points in the circuit, particularly atthe output.

More particularly, the code converter 10 of FIG. 1 receives an inputsignal X at a first sample rate of 1/τ samples per second at the inputto first stage 11, and generates therefrom an output signal Y at theoutput of the third stage including a slower sample rate which is (1/N)that of the input signal X sample rate. With code converter 10 of FIG.1, two clocks C₁ and C₂ are used for timing purposes in certain circuitswithin the three stages, with the pulse sequences of these two clocks,and an inverted clock sequence C₂, being illustrated in FIG. 2. As shownin FIG. 2, clock pulses of clock C₁ correspond to the digital samplevalue rate (1/τ) within each group of N samples of input signal X, whilethe clock C₂ includes pulses which are "N" times slower than that of theinput signal sample rate and correspond to the sample rate of the outputsignal Y. As stated above, clock C₂ is merely the inverse of clock C₂ .

In the code converter of FIG. 1, the input signal X at the sample rate(1/τ), is received at an adder 20₁ of first stage 11. Each digitalsample value of input signal X is added to the contents of a register21₁ in adder 20₁ every τ seconds, and the output of adder 20₁ is gatedto register 21₁ via a gate 22₁ which is clocked by clock signal C₂.Concurrent with this occurrence in first stage 11, the output from adder20₁ is sent to adder 20₂ of second stage 12 where this output from adder20₁ is added to the current contents of register 21₂ every τ seconds.The resultant output from adder 20₂ is then gated back into register 21₂via gate 22₂ which is enabled by clock C₂. This output from adder 20₂ isalso sent to adder 20₃ in third stage 13 to which the current contentsof register 21₃ is added every τ seconds before the resultant sum isused to update register 21₃ via gate 22₃.

During the N^(th) sample period of each group of N samples, the input toeach of adders 20₁, 20₂ and 20₃ is added to the current contents ofregisters 21₁, 21₂ and 21₃, respectively. However, during this N^(th)sample period, clock C₂ inhibits gates 22₁, 22₂ and 22₃ for one sampleperiod, and clock C₂ diverts the resultant output sums from adders 20₁,20₂ and 20₃ to registers 24₁, 24₂ and 24₃, respectively. Therefore,during the N^(th) sample period of each group, registers 21₁, 21₂ and21₃ are cleared because they have no input as a result of the inhibitingof these registers by gates 22₁, 22₂ and 22₃.

These above-described actions result in the sum of N consecutive inputsample values of a group being placed in register 24₁ at regularintervals of Nτ seconds. This sum in register 24₁ may be expressed as:##EQU1## where x(nτ) represents the input samples, z⁻¹ is a delay τ, andz^(-N) is a delay Nτ. The cycle then recommences in first stage 11.Concurrent with register 24₁ receiving the sum of N consecutive inputsample values of a group as expressed in Equation (1), a sum of partialsums of the input samples of a group, as found at the output of adder20₂ during the N^(th) sample period, is placed in register 24₂, whichsum of partial sums can be expressed as: ##EQU2## Concurrent therewith,a sum of partial sums of partial sums from the input sample group, asfound at the output of adder 20₃ during the N^(th) sample period of agroup, is placed in register 24₃, which sum of partial sums of partialsums may be expressed as: ##EQU3##

At the outputs of registers 24₁, 24₂ and 24₃ are three separate signalsdesignated Y₁, Y₆ and Y₁₀, respectively, that are further processed inthe three stages 11-13 at the desired output rate and combined in adder37 to produce the net output y where ##EQU4## Three practical detailssignificantly simplify the circuits needed for this decimation or codeconversion. First, the input words are short, usually 1-bit long, so theaccumulations need not be large, but they operate at high speed. Bits ofthe words are usually carried in parallel on separate wires. Second,words in registers 24₁ to 24₃ occur at a low rate and they may beoutputted from registers 24₁, 24₂ and 24₃ on single wires as bits intime sequence so that all of the circuits that follow are simple.Finally, the decimation ratio is usually a power of two, 2^(n),therefore, multiplying by N or (N/2) is simply a shift in significanceof the word involving no arithmetic operation.

In operation, it will be assumed hereinafter that an output word isgenerated for every 8 input samples (N=8), occurring at the C₁ clockrate. For purposes of explanation, a particular sequence of 8 inputsamples will be designated X₁ to X₈. These eight digital sample valuesare accumulated, as will be described hereinafter, to form compositedigital sample values at each of registers 24₁, 24₂ and 24₃ which havebeen designated Y₁, Y₆ and Y₁₀, respectively. FIGS. 3-13 show how eachof the 8 input digital sample vaues of the group received at the inputare weighted overall, including any weights used for a sample value atall prior locations, at the location associated with that weightingdiagram within the three stages 11-13, to achieve the sinc³ processingand produce the accumulated single digital output value forming thefinal single digital output value Y. It should be realized that each ofthe input digital sample values X₁ to X₈ in an input group has aseparate amplitude or value indication. Therefore, for each locationassociated with FIGS. 3-13, the overall resultant digital value Y_(i) atthe associated code converter location is conceptually obtained byapplying the indicated overall weight value shown in the associatedFigure to each of the corresponding one of the eight exemplary originalinput digital sample values for accumulation of the resultant digitalvalue.

In FIG. 1, the output signal Y₁ from register 24₁, in first stage 11,includes a single digital value represented by an accumulation of theN=8 exemplary sequential input digital sample values X₁ to X₈ of eachinput group weighted with a separate corresponding unity weight W₁ toW₈, respectively, as shown in FIG. 3. The output signal Y₁ from register24₁ is then multiplied by N/2 in multiplier 25 to produce a digitalvalue Y₂ representative of the accumulation of the 8 exemplarysequential input digital sample values with an overall weight, as shownin FIG. 4, including all weights used from the input through multiplier25. More particularly, for the exemplary condition of N=8, theaccumulated value Y₂ is derived from an accumulation of the eightdigital samples of a group individually weighted by unity to produce Y₁,as shown in FIG. 3, and then multiplied by individual weights of (N/2)effectively applid to each digital sample by multiplier 25 to form theoverall single accumulated value Y₂. Therefore, FIG. 4 shows the overallweight of value 4 applied up to that point to each corresponding inputdigital sample value of a group in the original accumulation signal Y₁times the weights applied by multiplier 25 to produce the value Y₂.

The Y₂ output signal is then multiplied by N in multipler 26 to producea digital value Y₃ which is an accumulation of the eight exemplarysequential input digital sample values weighted overall as shown in FIG.5. The Y₃ output digital value is added in adder 27 to the outputdigital value Y₁₀ from register 24₃ in third stage 13 to produce a Y₄digital value which is the accumulation of the eight exemplarysequential digital input samples weighted overall as shown in FIG. 6. Insubtracter 28, the Y₈ digital value from second stage 12 is subtractedfrom the Y₄ digital value to produce an output digital value Y₅ fromfirst stage 11 which is delayed by one output word time period Nτ indelay unit 29.

In second stage 12, the output digital value Y₆ from register 24₂ is anoverall digital value of the eight exemplary sequential input wordsample weighted as shown in FIG. 8. This digital value is multiplied byN in multiplier 30 to generate an overall digital value Y₇ which is anaccumulation of the eight exemplary sequential digital input samplesweighted overall as shown in FIG. 9. The Y₂ digital value frommultiplier 25 in first stage 11 is added in adder 31 to the Y₇ digitalvalue to generate an overall digital value Y₈ which is an accumulationof the eight input digital samples weighted overall as shown in FIG. 10.Second stage 12 includes a combination of (1) the Y₃ digital valueadded, in adder 32, to the delayed Y₅ output digital value from firststage 11; (2) the output digital value from adder 32 added, in adder 33,to the Y₈ digital value; and (3) the output digital value Y₁₀ from thirdstage 13, which has been weighted by N in multiplier 34, subtracted fromthe output digital value from adder 33 in subtracter 35. The combinationof these digital values before being added to the Y₅ digital value fromfirst stage 11 is an overall digital value designated Y₉ which is anaccumulated digital value of the exemplary sequential eight inputdigital samples weighted overall as shown in FIG. 11. Therefore, theoutput digital value from the first, second and third stages 11-13correspond to the exemplary sequential eight input digital samplesweighted as shown in FIGS. 7, 11, and 12, respectively, and make up theoutput digital value Y from code converter 10 at the output of adder 37.

It should be understood that the exemplary eight sequential input signalsamples forming an input group and arriving at the input to adder 20₁ infirst stage 11 generate (1) the Y₅ output digital sample from firststage 11 during a first output word period Nτ; (2) the Y₉ output digitalvalue from second stage 12 during a second next subsequent output wordperiod Nτ; and (3) the Y₁₀ output digital value from third stage 13during a third next subsequent output word period Nτ because thesequential accumulations associated with an input group of N samples aretransferred between the three stages based at the C₂ clock rate shown inFIG. 2. Therefore, by delaying the Y₅ output from first stage 11 by oneoutput word period Nτ in delay 29 and adding the delayed Y₅ output tothe Y₉ output from second stage 12 and then delaying the resultantdigital value by another output word period in delay 36 before addingthe delayed resultant value to the Y₁₀ output from third stage 13, aresultant output digital value Y is obtained which is the accumulationof the eight input digital samples weighted as shown in FIG. 13 in thethree stages.

Since a new digital value is outputted once every output word periodfrom each of the three stages, and it takes three output word periodsbefore the overall accumulations in the three stages are combined toproduce an associated single digital value output Y, the result of threesequential output words can be depicted as shown in FIG. 14. The topportion of FIG. 14 depicts three sequential weighting curves 40-42 ofFIG. 13 corresponding to an exemplary first to third input groupsequence, respectively, each sequential weighting curve 40-42 startingone output word period apart. The output digital value 43 associatedwith weighting curve 40 of the first output word, in the three outputword sequence, occurs at the conclusion of the three output word periodnecessary for the sinc³ processing in the three stages of code converter10, followed by the output digital values 44 and 45 associated withweighting curves 41 and 42, respectively, spaced by one output wordperiod Nτ. From the above description it can be seen that in accordancewith the present invention, the code converter, or decimator, of FIG. 1provides sinc³ processing.

What is claimed is:
 1. A digital-to-digital code converter comprising:aninput terminal for receiving an input signal including a series ofgroups, where each group comprises a sequence of N separate digitalsample values occurring at a first predetermined rate and N>1; an outputterminal; and processing means responsive to the input signal at theinput terminal for performing sinc³ processing on the N digital samplevalues of each input group to generate therefrom a representative singledigital output value for each input group at a second predetermined rateat the output terminal, the second predetermined rate being slower thanthe first predetermined rate, the processing means comprising, first,second and third accumulation means disposed in a first, a second and athird stage, respectively, of the code converter, the accumulation meansand the stages being arranged in cascade and each accumulation meansincludes means for adding each digital sample value received from thepreceding stage during a current group period to a current accumulatedvalue of the digital sample values received previously during thatcurrent group period; and first, second and third subprocessing meansdisposed in the first, second and third stages, respectively, forprocessing a resultant overall accumulated value obtained by theassociated accumulation means at the end of each group period andgenerating a separate appropriately weighted intermediate valueassociated with each input group period, which intermediate values fromeach of the three stages, and associated with an input group, arecombined to provide the sinc³ processed representative single digitaloutput value from the code converter.
 2. A digital-to-digital codeconverter according to claim 1 wherein the first, second and thirdaccumulation means each comprise:a storage means for temporarily storingthe accumulated value of the N output values received from theimmediately prior stage during a current group period; an adder foradding each output value received from the immediately prior stage ofthe code converter with a current accumulated value stored in thestorage means to generate a new overall accumulated value which is usedto update the storage means; and gating means for gating each of the newoverall accumulated values during a current group period into thestorage means and for clearing the storage means at the end of eachgroup period.
 3. A digital-to-digital code converter according to claim1 or 2 wherein the first, second and third subprocessing means eachcomprise:a storage means for storing the overall accumulated valueobtained from the accumulation means in the same stage at the end ofeach group period; and means responsive to the overall accumulated valuestored in the subprocessing means storage means for generating theappropriately weighted intermediate value associated with that stage forsubsequent combination with the appropriately weighted intermediatevalues of the other stages associated with the same input group toproduce the sinc³ processed representative single digital output valuefrom the code converter.